Memory systems typically utilize circuits which detect memory error signals from parity or error detection circuitry and which extend or stretch all memory cycles until an error detection delay interval has elapsed. A typical example of such a pulse expanding circuit is taught by Bennett et al. in U.S. Pat. No. 4,050,096 assigned to the assignee hereof. Although slow memory devices may be used in such a system, stretching all memory cycles substantially decreases the memory system performance by making the cycles much slower. A known alternative method to provide time for error detection in a memory system is to add wait cycles and postpone data processing cycles until the data error or errors have been detected. When wait cycles are inserted, fast memory devices are required to facilitate detection of errors and to keep from substantially delaying the output of the memory system. When either method is used, overall system speed is greatly reduced.